The present invention relates generally to memory designs, and more particularly to an improved memory design that uses a process of fabricating a memory cell and a logic device.
Semiconductor dynamic random access memory (DRAM) design is a technology driver for much of the integrated circuit (IC) industry. Structures and process originated for DRAMs are applied widely. A DRAM element stores a bit of data in a capacitor that is accessed through a metal-oxide-semiconductor field-effect-transistor (MOSFET) that is switched by a word line. A bit of data is available to a MOSFET from a bit line. When the word line turns on a MOSFET, the data stored in the capacitor can be read through the bit line.
The layout of the circuit on the semiconductor chip and the design of the capacitors are strong determinants of the area efficiency, and therefore cost, of a DRAM chip. In semiconductor structure, DRAM capacitors have typically been either buried or stacked. Buried capacitors are usually placed in trenches in the semiconductor substrate. The deeper the trench, the more area its vertical surfaces have available for larger capacitance values. This still requires significant chip area. Stacked capacitors can be either polycrystalline silicon (poly) or metal-insulator-metal (MIM). The MIM capacitors are embedded in the oxide layers above the active surface of the chip.
A bit line contact reaches the active chip surface downward through a metal-filled contact via to a contact that is common to two MOSFETs. As one of the two MOSFETs is switched by a word line, the bit line can either write a bit to a capacitor that is attached to the other contact of the MOSFET or it can read a bit from the capacitor. So, the bit line contact is tightly placed between the two capacitors that are constructed above MOSFET contacts. Contact must also be made to the upper plate of each capacitor, thereby taking additional space. The requirement for contact space is in conflict with a requirement for a capacitor with a large surface area to produce a large capacitance value. As design geometries shrink, an insufficient contact-to-capacitor overlap margin, which typically results in poor window conditions, becomes a significant problem.
A stacked capacitor can be made taller to achieve larger capacitance values. In such a design, which typically involves what is known as a crown-shaped capacitor structure, insulator layers are extra thick in order to successfully cover the topology created by the capacitor structure. By using an extra thick insulator layer, the use of deep vias with high aspect ratio is required. However, such vias are difficult to produce and difficult to fill with metal. In addition, since stacked capacitors are typically constructed by processes and structures that are not directly compatible with dual damascene processes and structures, their realization requires extra process steps, extra processes, extra memory cell size, extra photomasks, and therefore, extra costs.
In conventional realizations, the structure of the contact vias is typically the same in the logic region as it is in the memory cell region. Above the contact via layer, an etch stop layer begins the dual damascene layers. Since the dual damascene structure is already used in the logic region, it is desirable to utilize this structure in the memory cell region as well.
As such, desirable in the art of memory designs are improved process that integrates fabrication of a logic device and memory cell, that improves the high aspect ratio problem in the conventional art, and that reduces the thermal budgets.